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www.fairchildsemi.com rev. 1.0.5 7/22/04 features drives n-channel high-side and low-side mosfets in a synchronous buck con?uration 12v high-side and 12v low-side drive internal adaptive ?hoot-through?protection integrated bootstrap diode for high-side drive ? ast rise and fall times switching frequency up to 500khz ?d input for output disable ?allows for synchronization with pwm controller soic-8 package ? v ailable in low thermal resistance mlp package applications multi-phase vrm/vrd regulators for microprocessor power high current/high frequency dc/dc converters high power modular supplies general description the fan5009 is a dual, high frequency mosfet driver, speci?ally designed to drive n-channel power mosfets in a synchronous-recti?d buck converter. these drivers, combined with a fairchild multi-phase pwm controller and power mosfets, form a complete core voltage regulator solution for advanced microprocessors. the fan5009 drives the upper and lower mosfet gates of a synchronous buck regulator to 12v gs . the upper gate drive includes an integrated boot diode and requires only an e xternal bootstrap capacitor (c boot ). the output drivers in the fan5009 have the capacity to ef?iently switch power mosfets at frequencies up to 500khz. the circuits adaptive shoot-through protection prevents the mosfets from conducting simultaneously. the fan5009 is rated for operation from 0? to +85? and is available in low-cost soic-8 or mlp packages. t ypical application figure 1. typical application. sw fan5009 12v vcc overlap protection circuit 6 5 7 8 1 pwm 2 c boot boot vcc 4 q1 q2 c vcc c out l1 v out 3 hdrv ldrv pgnd od f an5009 dual bootstrapped 12v mosfet driver
2 rev. 1.0.5 7/22/04 fan5009 product specification pin con?uration pin de?itions functional block diagram pin # pin name pin function description 1 boot bootstrap supply input. provides voltage supply to high-side mosfet driver. connect to bootstrap capacitor. see applications section. 2 pwm pwm signal input. this pin accepts a logic-level pwm signal from the controller. 3od output disable. when low, this pin disables fet switching (hdrv and ldrv are held low). 4 vcc power input . +12v chip bias power. bypass with a 1? ceramic capacitor. 5 ldrv low side gate drive output. connect to the gate of low-side power mosfet(s). 6 pgnd power ground. connect directly to source of low-side mosfet(s). 7sw switch node input . connect as shown in figure 1. sw provides return for high-side bootstrapped driver and acts as a sense point for the adaptive shoot-thru protection. 8 hdrv high side gate drive output ? connect to the gate of high-side power mosfet(s). boot pwm od vcc fan5009 1 2 3 4 8 7 6 5 hdrv sw pgnd ldrv FAN5009M 8- pin so-8 package boot pwm od vcc fan5009 1 2 3 4 8 7 6 5 hdrv paddle (ground) sw pgnd ldrv FAN5009Mp 8-pin mlp package (paddle should be connected to ground or left floating) pwm 2 od 3 2.2 1.2 1 boot vcc 4 sw 7 + vcc 6 5 ldrv pgnd 8 hdrv 1.2
product specification fan5009 rev. 1.0.5 7/22/04 3 absolute maximum ratings stresses above those listed in ?bsolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational section of this speci?ation is not implied. exposure to the absolute maximum rating conditions for e xtended periods may affect device reliability. absolute maximum ratings apply individually, not in combination. unless otherwise speci?d, voltages are referenced to pgnd. notes: 1. for transient derating beyond the levels indicated, refer to the graphs on page 7. thermal information recommended operating conditions p arameter min. max. units vcc to pgnd ?.3 15 v pwm and od pins ?.3 5.5 v sw to pgnd continuous ? 15 v tr ansient ( t=100nsec, f 500khz) ? (1) 25 v boot to sw ?.3 15 v boot to pgnd continuous ?.3 30 v tr ansient ( t=100nsec, f 500khz) 33 (1) v hdrv v sw ? v boot +0.3 v ldrv continuous ?.5 v cc +0.3 v tr ansient ( t=200nsec) ? (1) v p arameter min. typ. max. units junction temperature (t j )0 150 ? storage temperature ?5 150 ? lead soldering temperature, 10 seconds 300 ? vapor phase, 60 seconds 215 ? infrared, 15 seconds 220 ? power dissipation (p d ) t a = 25? 715 mw thermal resistance, so8 ?junction to case jc 40 ?/w thermal resistance, so8 ?junction to ambient ja 140 ?/w thermal resistance, mlp ?junction to paddle jc 4 ?/w p arameter conditions min. typ. max. units supply voltage vcc vcc to pgnd 10 12 13.5 v ambient temperature (t a )085 ? junction temperature (t j )0 125 ?
4 rev. 1.0.5 7/22/04 fan5009 product specification electrical speci?ations v cc = 12v, and t a = 25? using circuit in figure 2 unless otherwise noted. the ?denotes speci?ations which apply ov er the full operating temperature range. figure 2. test circuit p arameter symbol conditions min. typ. max. units input supply vcc voltage range v cc 6.4 12 13.5 v vcc current i cc od = 0v 3.5 8 ma bootstrap diode continuous forward current i f(avg) ?5ma reverse breakdown voltage v r ?5 v reverse recovery time 2 t rr 10 ns forward voltage 2 v f i f = 10ma 0.8 0.95 v od input input high voltage v ih (od ) 2.5 v input low voltage v il (od ) 0.8 v input current i od od = 3.0v ?00 +300 na propagation delay 2 t pdl(od ) see figure 3 30 40 ns t pdh(od ) 30 45 ns pwm input input high voltage v ih(pwm) 3.5 v input low voltage v il(pwm) 0.8 v input current i il(pwm) ?1 +1 a high-side driver output resistance, sourcing current r hup v boot ? sw = 12v 3.8 4.4 ? output resistance, sinking current r hdn v boot ? sw = 12v 1.4 1.8 ? transition times 2,4 t r(hdrv) see figure 2 40 55 ns t f(hdrv) 20 30 ns propagation delay 2,3 t pdh(hdrv) see figure 2, and 4 50 65 ns t pdl(hdrv) 25 40 ns fan5009 1 2 3 4 8 7 6 5 hdrv sw pgnd ldrv boot pwm od vcc 12v 33k 10k 3000pf 3000pf 1 f
product specification fan5009 rev. 1.0.5 7/22/04 5 electrical speci?ations (continued) notes: 1. all limits at operating temperature extremes are guaranteed by design, characterization and statistical quality control 2. ac specifications guaranteed by design/characterization (not production tested). 3. for propagation delays, ?pdh?refers to low-to-high signal transition and ?pdl?refers to high-to-low signal transition 4. transition times are defined for 10% and 90% of dc values figure 3. output disable timing figure 4. adaptive gate drive timing p arameter symbol conditions min. typ. max. units low-side driver output resistance, sourcing current r lup 3.4 4.0 ? output resistance, sinking current r ldn 1.4 1.8 ? transition times 2,4 t r(ldrv) see figure 2 40 50 ns t f(ldrv) 20 30 ns propagation delay 2,3 t pdh(ldrv) see figures 2, 4 20 30 ns t pdl(ldrv) 25 40 ns t pdh(odrv) see adaptive gate drive circuit description 240 ns v i l(od) t pdl(od) v i h(od) t pdh(od) ldrv / hdrv od v ih(pwm) t pdl (ldrv) ldrv pwm hdrv-sw 1.2v v il(pwm) t pdl (hdrv) 2 .2v t pdh(ldrv) sw t pdh (hdrv)
6 rev. 1.0.5 7/22/04 fan5009 product specification t ypical characteristics 0 10 20 30 40 50 60 70 1,000 2,000 3,000 4,000 5,000 c load (pf) time (nsec) c load (pf) time (nsec) t fall t rise t rise 0 10 20 30 40 50 60 70 1,000 2,000 3,000 4,000 5,000 t fall 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 025507 5 100 125 temperature ( c) z (normalized) source sink 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 0255 075 100 125 temperature ( c) z (normalized) pwm hdrv ldrv pwm hdrv ldrv source sink gate drive rise and fall times hdrv rise/fall times vs. c load ldrv rise/fall times vs. c load hdrv impedance vs. temperature (normalized) ldrv impedance vs. temperature (normalized)
product specification fan5009 rev. 1.0.5 7/22/04 7 t ypical characteristics (continued) i cc vs. frequency 0 4 8 12 16 20 0 100 200 300 400 500 frequency (khz) i cc (ma) boot diode v negative ldrv voltage transient boot voltage transient f vs. i f 400 600 800 1,000 1,200 1,400 1,600 11 0 100 1000 i f (ma) v f (mv) 25 c 85 c 125 c boot diode peak i f 0 1 2 3 4 5 6 7 8 9 10 50 75 100 125 150 175 200 t on at 500khz (nsec) peak i v boot ?nd (v) f (a) 30 31 32 33 34 35 36 0 100 200 300 400 500 transient duration (nsec) v ldrv (v) 0.0 -1.0 -2.0 -3.0 -4.0 -5.0 -6.0 0 100 200 300 400 500 transient duration (nsec) negative sw voltage transient v sw (v) transient duration (nsec) -13 -12 -11 -10 -9 -8 -7 -6 -5 -4 -3 0 100 200 300 400 500 ~1.2j per cycle
8 rev. 1.0.5 7/22/04 fan5009 product specification circuit description the fan5009 is a dual mosfet driver optimized for driv- ing n-channel mosfets in a synchronous buck converter topology. a single pwm input signal is all that is required to properly drive the high-side and the low-side mosfets. each driver is capable of driving a 3nf load at speeds up to 500khz. f or a more detailed description of the fan5009 and its features, refer to the internal block diagram and figure 1. low-side driver the low-side driver (ldrv) is designed to drive a ground- referenced low r ds(on) n-channel mosfets. the bias for ldrv is internally connected between vcc and pgnd. when the driver is enabled, the drivers output is 180?out of phase with the pwm input. when the fan5009 is disabled (od = 0v), ldrv is held low. high-side driver the high-side driver (hdrv) is designed to drive a ?ating n-channel mosfet. the bias voltage for the high-side driver is developed by a bootstrap supply circuit, consisting of the internal diode and external bootstrap capacitor (c boot ) . during start-up, sw is held at pgnd, allowing c boot to charge to vcc through the internal diode. when the pwm input goes high, hdrv will begin to charge the high-side mosfets gate (q1). during this transition, charge is removed from c boot and delivered to q1s gate. as q1 turns on, sw rises to v in , forcing the boot pin to v in +v c(boot) , which provides suf?ient v gs enhancement for q1. to complete the switching cycle, q1 is turned off by pulling hdrv to sw. c boot is then recharged to vcc when sw f alls to pgnd. hdrv output is in phase with the pwm input. when the driver is disabled, the high-side gate is held low. adaptive gate drive circuit the fan5009 embodies an advanced design that ensures minimum mosfet dead-time while eliminating potential shoot-through (cross-conduction) currents. it senses the state of the mosfets and adjusts the gate drive, adaptively, to ensure they do not conduct simultaneously. refer to figure 4 for the relevant timing waveforms. to prevent overlap during the low-to-high switching transi- tion (q2 off to q1 on), the adaptive circuitry monitors the v oltage at the ldrv pin. when the pwm signal goes high, q2 will begin to turn off after some propagation delay (t pdl(ldrv) ). once the ldrv pin is discharged below ~1.2v, q1 begins to turn on after adaptive delay t pdh(hdrv) . to preclude overlap during the high-to-low transition (q1 off to q2 on), the adaptive circuitry monitors the voltage at the sw pin. when the pwm signal goes low, q1 will begin to turn off after some propagation delay (t pdl(hdrv) ). once the sw pin falls below ~2.2v, q2 begins to turn on after adaptive delay t pdh(ldrv) . additionally, v gs of q1 is monitored. when v gs(q1) is discharged below ~1.2v, a secondary adaptive delay is initi- ated, which results in q2 being driven on after t pdh(odrv) , regardless of sw state. this function is implemented to ensure c boot is recharged each switching cycle, particularly for cases where the power convertor is sinking current and sw voltage does not fall below the 2.2v adaptive threshold. secondary delay t pdh(odrv) is longer than t pdh(ldrv) . application information supply capacitor selection f or the supply input (v cc ) of the fan5009, a local ceramic bypass capacitor is recommended to reduce the noise and to supply the peak current. use at least a 1?, x7r or x5r capacitor. keep this capacitor close to the fan5009 v cc and pgnd pins. bootstrap circuit the bootstrap circuit uses a charge storage capacitor (c boot ) and the internal diode, as shown in figure 1. selec- tion of these components should be done after the high-side mosfet has been chosen. the required capacitance is determined using the following equation: where q g is the total gate charge of the high-side mosfet, and ? v boot is the voltage droop allowed on the high-side mosfet drive. for example, the q g of the fdd6696 is about 35nc @ 12v gs . for an allowed droop of ~300mv, the required bootstrap capacitance is 100nf. a good quality ceramic capacitor must be used. the average diode forward current, i f(avg) , can be estimated by: where f sw is the switching frequency of the controller. the peak surge current rating of the internal diode should be checked in-circuit, since this is dependent on the equivalent impedance of the entire bootstrap circuit, including the pcb traces. for applications requiring higher i f , an external diode may be used in parallel to the internal diode. c boot q g ? v boot ---------------------- = (1) i favg () q gate f sw = (2)
product specification fan5009 rev. 1.0.5 7/22/04 9 thermal considerations t otal device dissipation: where p q represents quiescent power dissipation: where f sw is switching frequency (in khz). p r is power dissipated in the bootstrap recti?r: where q g1 is total gate charge of the upper fet (q1) for its applied v gs . v f for the applied i f(avg) can be graphically determined using the datasheet curves, where: p hdrv represents internal power dissipation of the upper fet driver. where p h(r) and p h(f) are internal dissipations for the rising and falling edges, respectively: where: as described in eq. 8 and 9 above, the total power consumed in driving the gate is divided in proportion to the resistances in series with the mosfet's internal gate node as shown below: figure 5. driver dissipation model r g is the polysilicon gate resistance, internal to the fet. r e is the external gate drive resistor implemented in many designs. note that the introduction of r e can reduce driver power dissipation, but excess r e may cause errors in the ?daptive gate drive?circuitry. for more information please refer to fairchild app note an-6003, ?hoot-through?in synchronous buck converters. p ldrv is dissipation of the lower fet driver. where p h(r) and p h(f) are internal dissipations for the rising and falling edges, respectively: where: layout considerations use the following general guidelines when designing printed circuit boards (see figures 6 and 7): 1. trace out the high-current paths and use short, wide (>25 mil) traces to make these connections. 2. connect the pgnd pin of the fan5009 as close as possible to the source of the lower mosfet. 3. the v cc bypass capacitor should be located as close as possible to v cc and pgnd pins. 4. use vias to other layers when possible to maximize thermal conduction away from the ic. figure 6. external component placement recommendation for so8 package (not to scale) p d p q p r p hdrv p ldrv ++ + = (3 ) p q v cc 4ma + 0.036 f sw 100 () [] = (4) p r v f f sw q g1 = (5) i f avg () f sw q g1 = (6 ) p hdrv p hr () p hf () + = (7) p hr () p q1 r hup r hup r e r g ++ ---------------------------------------- = (8 ) p hf () p q1 r hdn r hdn r e r g ++ ---------------------------------------- - = (9 ) p q1 1 2 -- - q g1 v gs q1 () f sw = (10 ) hdrv q1 g r g r e r hup boot sw r hdn s p ldrv p lr () p lf () + = (11) p lr () p q2 r lup r lup r e r g ++ --------------------------------------- - = (12 ) p lf () p q2 r ldn r hdn r e r g ++ ---------------------------------------- - = (13 ) p q2 1 2 -- - q g2 v gs q2 () f sw = (14 ) 1 2 3 4 8 7 6 5 c boot c vcc
10 rev. 1.0.5 7/22/04 fan5009 product specification 5. the paddle on the mlp package is internally referenced to ground. it can be left ?ating or connected to ground. f or best thermal performance it should be connected to ground as shown in figure 7. figure 7. recommended layout for mlp package. also accepts so8 package (not to scale) 6. the recommended land pattern shown in the mlp mechanical dimensions will work with both mlp-8 and so-8 packages. the circuit in figure 1 illustrates a typical implementation of a single phase of a multi-phase buck converter for v core applications. for a complete vr10 design example, please refer to the fan5019 or fan5018 datasheets. 1 2 3 4 8 7 6 5 c boo t c vcc ground vias paddle
product specification fan5009 rev. 1.0.5 7/22/04 11 mechanical dimensions 0.150, 8 lead soic package 85 14 d a a1 ?c ccc c lead coplanarity seating plane e b l h x 45 c eh a .053 .069 1.35 1.75 symbol inches min. max. min. max. millimeters notes a1 .004 .010 0.10 0.25 .020 0.51 b .013 0.33 c .0075 .010 0.20 0.25 e .150 .158 3.81 4.01 e .228 .244 5.79 6.20 .010 .020 0.25 0.50 h .050 bsc 1.27 bsc h l .016 .050 0.40 1.27 0 8 0 8 3 6 5 2 2 n8 8 ccc .004 0.10 d .189 .197 4.80 5.00 notes: 1. 2. 3. 4. 5. 6. dimensioning and tolerancing per ansi y14.5m-1982. "d" and "e" do not include mold flash. mold flash or protrusions shall not exceed .010 inch (0.25mm). "l" is the length of terminal for soldering to a substrate. terminal numbers are shown for reference only. "c" dimension does not include solder finish thickness. symbol "n" is the maximum number of terminals.
12 rev. 1.0.5 7/22/04 fan5009 product specification mechanical dimensions 5mm x 6mm, 8 lead mlp package notes: b) dimensions are in millimeters. a) does not fully conform to jedec registration mo-229, dated 11/2001. c) dimensioning and tolerances per asme y14.5?994. land pattern recommendation top view side view bottom view 3.81 1.27 pin #1 ident. (optional) 1.27 typ 0.65 typ (1.00) 3.50 4.50 4.25 6.25 1.0 max c c c mc m 0.10 0.10 0.08 0.05 c ab 0.05 0.00 0.28?.40 4.25 1.75 3.25 1.25 0.75 0.35 seating plane a a a a a 1234 8765 (0.25) 6.0 b a 5.0 0.25 2x c 0.25 2x c
7/22/04 0.0m 001 stock#ds505009 ? 2004 fairchild semiconductor corporation life support policy fairchild? products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. fan5009 product specification ordering information pa rt number temperature range package packing FAN5009M 0? to 85? soic-8 rails FAN5009Mx 0? to 85? soic-8 tape and reel FAN5009Mpx 0? to 85? mlp-8 tape and reel

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